This invention relates to field effect transistors and in particular to such transistors fabricated in a III-V semiconductor, e.g. gallium arsenide.
With the increasing need to raise the device cut-off frequency, silicon is being replaced by compound semiconductors in the fabrication of high speed integrated circuits. The most commonly employed of these new materials is gallium arsenide. Conventionally field effect transistors (MESFET's) are fabricated in this material be selectively implanting an n-type channel region into a semi-intrinsic GaAs substrate, implanting heavily doped n.sup.+ type source and drain regions, and forming ohmic contacts to the source and drain. The gate metal, typically chromium/gold, is then defined between the source and drain regions. Further layers of gold may then be deposited to form interconnects, e.g., in the formation of an integrated circuit.
Of the photolithographic steps used in this process the most critical is that which defines the transistor gate. For high performance operation the gate metal strip must not only be narrow, typically 1 micron or less, but must also be separated from the source by a similar submicron dimension. This spacing requirement is necessary to minimize the parasitic series resistance between the source and channel of the transistor. It will be appreciated that the use of a photolithographic process with such critical dimensional tolerances results in a low yeild and/or excessive and variable series resistance.
In an attempt to overcome this problem a number of processes have been developed in which the source and drain regions are self aligned to the gate. In a typical process of this type a gate material that is stable at the temperature required for annealing the source/drain implant is employed. The gate is defined prior to the implantation step and the subsequent annealing. In the finished device there is then no gap between the low resistivity source region and the controlled channel. In practice this `zero gap` technique introduces further difficulties because the resulting diode between the gate and source has no blocking characteristic.